A Guide To The Cyrix Jalapeno Japaleno The Cyrix Jalapeno Processor Cyrix's 7th generation processor core, code-named Jalapeno, marks a departure from the traditional engineering approach that has been pursued by Cyrix in the past. Previously, in the 6th generation M1 and M2 cores, Cyrix had focused on designing a highly efficient processor core which could perform a high number of instructions per clock cycle. This approach had the advantage of allowing most x86 instructions to be executed in a single cycle. The Jalapeno on the other hand, has shortened pipelines that are optimized to achieve a high clock speed by eliminating circuit complexities that would otherwise limit its maximum clock frequency. Although the shortening of pipelines has the negative effect of allowing pipeline stalls to occur, additional execution units have been added to increase throughput and prevent dispatch stalls. The Jalapeno also features an integrated Northbridge interface and control circuitry and this has both the added benifit of reducing latency as well as allowing for the execution of speculative and anticipatory operations between the processor cache and the DRAM controller. The key features: Pipelines Tuned For High Clock Speeds Large On-chip Level 2 Cache Greater than 600MHz 3D Now! Instruction Set SIMD Processing 0.18 micron Manufacturing Process

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Last modified on August 10, 1997